Demonstration of a CXL Interconnect on a FPGA-based design

 

In this video, we demonstrate the PLDA XpressLINK Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon CPU as a host, connected to an FPGA board, instantiating PLDA’s CXL Controller and CXL.mem test design. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

 

 

 

Webinar: Verification of PCIe® 6.0 IP

 

With the draft specification available and the upcoming release of the final PCIe Gen 6 specification, system designers are beginning to plan how to build the specification’s new features into their products.

In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.

Rambus to Acquire PLDA, Extending Leadership with Cutting -Edge CXL™ and PCI Express® Digital IP

  • Expands digital controller IP portfolio with complementary CXL 2.0, PCIe® 5.0 and PCIe 6.0 controller and switch IP
  • Enables integrated interface subsystem solutions for data center, artificial intelligence and machine learning (AI/ML), and High Performance Computing (HPC)
  • Provides critical building blocks for Rambus CXL Memory Interconnect Initiative to advance high-bandwidth connectivity

 

Reducing CXL Latency with PLDA and AnalogX

 

Certain applications and hardware types -- emerging memory, artificial intelligence/machine learning, and cloud servers, to name a few -- can realize significant performance advantages when a low latency interface is employed. The CXL (Compute Express Link™) standard was developed specifically as a low latency offshoot of the ever-popular PCIeTM (PCI ExpressTM), and is finding its footing in many of the applications listed.

Let’s compare typical latency of existing standards first. Data shown below is gathered from a variety of industry sources: 

Why PCIe 6.0 Now?

In our last article, we address some of the changes in the PCIe 6.0 specification versus prior generations. Of note in that was that the release cadence of specifications has greatly increased.

As a reminder of how the PCIe specification has evolved:

Figure 1: PCIe Evolution

 

Looking at the table above, you can see that pre-4.0, specifications were updated every 4.6 years on average. However, since 4.0, the cadence has greatly increased, with a release every 2 years. A logical question here might be ‘why have 5.0 and 6.0 come so fast?’

PLDA and AnalogX Announce Market-leading CXL 2.0 Solution featuring Ultra-low Latency and Power

 

Highlights:

  • Optimized integration of PLDA CXL 2.0 controller and AnalogX ultra low power PHY reduces latency by over 50% and power by 40% compared to leading competitive solutions
  • Improves system performance at no extra cost, while pre-configured integration reduces design time and speeds time-to-market

PLDA, the leading developer of high-speed interconnect silicon IP, and AnalogX, the leading provider of low power multi-standard connectivity SerDes IP solutions, today announced an optimized integration of PLDA CXL™ 2.0 controller and AnalogX 32G-MR PHY that reduces latency by 50% and power consumption by 40% compared to leading competitive solutions. 

On PCIe 6.0

Today, PLDA announced our PCIe 6.0 controller IP. This announcement builds on PLDA’s track record of being the high speed interface IP provider of choice.

As PCIe 6.0 is quite new, let’s run through a bit about how it differs from previous generations, and why this should matter to a system designer or chip architect as they consider their next generation designs.

Webinar: "Preparing for PCIe 6.0"

 

As the need for data has exploded driven by applications like AI/ML and automotive, the semiconductor industry, led by PCI-SIG, is preparing for the final release of the PCIe 6.0 specification and all the changes it entails.

In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

What you will learn:

- what is PCIE 6.0
- how does it differ from past generations
- design considerations when planning with PCIe 6
- verification implications of a PCIe 6 design

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