Video description of vDMA-AXI IP

The explosion in data traffic due to the advent of Artificial Intelligence, machine learning, automotive and IoT prompts for new System-on-Chip architectures that allow system developers to build high-performance applications that are able to ingest and process huge amounts of heterogeneous data.

 

 

Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms

1. Introduction

As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc.

The transition to PCIe 4.0 and 5.0 with increasing PCIe signaling speeds (16GT/s and 32GT/s) also augments the risk of errors due to tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g. crosstalk, line attenuation, jitter, etc.).

Brite Semiconductor, Naneng Microelectronics, and PLDA Collaborate to Release Complete PCIe 2.0/3.0 Solution

Shanghai, China—Dec 11, 2018

Brite Semiconductor (“Brite”), a world-leading ASIC design service and DDR controller/PHY IP provider headquartered in Shanghai, China, today announced their collaboration with Naneng Microelectronics and PLDA to deliver a complete PCIe 2.0/3.0 solution based on SMIC’s 40nm and 55nm process technology.

Guosheng Wu, CEO of Naneng Microelectronics, said, “Collaboration between Naneng and Brite can effectively reduce the risks and costs of SoC design by providing a low power consumption and small-area PCIe-2.0/3.0 solution based on SMIC’s 40nm and 55nm process, that meets the latest PIPE specifications and supports 2.5G and 5G data rate. We are looking forward to working with Brite to provide customers with a global solution that offers high performance and low cost, while complying with the relevant standards.”

PLDA and Samtec Demonstrate PCIe 4.0 Communication over Twinax Cables Allowing Full 16GT/s PCIe 4.0 Bandwidth at Minimal Manufacturing Cost

PLDA, the industry leader in PCI Express® controller IP solutions and Samtec, a privately held $800MM global manufacturer of a broad line of electronic interconnect solutions, today announced a demo of their combined PCIe 4.0 solution that delivers full PCIe 4.0 bandwidth (16 GT/s) over copper or optical fiber at minimal cost.

The solution is based on a PLDA PCIe 4.0 acquisition board running PLDA’s PCIe 4.0 controller IP combined with Samtec’s FireFly™ Micro Flyover System™. This demo suggests a solution to overcoming the inherent limitations of maintaining PCIe 4.0 performance over long distances without changing the motherboard technology or using costly retimers.

PLDA Offers XpressRICH PCIe and CCIX Controller IP Through SiFive DesignShare Program

SAN MATEO, Calif., Nov. 26, 2018 -- SiFive, the leading provider of commercial RISC-V processor IP, today announced that PLDA, the leader in PCIe and CCIX Controller IP solutions has joined the DesignShare™ ecosystem. Through this collaboration, PLDA will provide its rich suite of XpressRICH core IP that enables high-speed connectivity solutions for many applications like enterprise storage, networking, high-performance computing and artificial intelligence to name a few.

PCIe 4.0 Communication over Optical Fiber and TWINAX Cables

As cloud computing and deep learning accelerators drive faster advances in the PCIe roadmap, existing hardware designs cannot support the higher speed signals over the same distances. The PCIe 1.0 specification allowed signals to travel as much as 20 inches over traces in mainstream FR4 boards, even while passing through two connectors. In contrast, today’s quicker 16 GT/s PCIe 4.0 signals will peter out in under six inches and without going over any connectors.

 

 

Come & meet us at ICCAD China 2018

 

ICCAD China 2018 - November 29-30
Zhuhai International Convention & Exhibition Center

Come and meet the PLDA Team at CSIA-ICCAD 2018 Annual Conference & Zhuhai IC Industry Innovation and Development Summit show in Zhuhai !


This free event provides a great opportunity for you to discover PLDA's latest PCIe solutions, such as :

Gen-Z Primer for Early Adopters

Computer systems as we know them have been built on the paradigm that the CPU-memory pair is fast while network and storage are slow. Over the years, these components developed their own language and interfaces that require layers of software to translate memory commands into network and storage commands and vice versa.

Until now, the speed of the CPU-memory pair relative to network and storage I/O was such that these software layers had minimal impact on system performance.

However, with Moore’s law in full effect, network and storage technologies are quickly catching up with CPU-memory speeds and the burden of generations of software layers now becomes significant.

PLDA and MegaChips announce a cooperation to design PCIe controllers and PCIe PHY IP on TSMC’s 16nm Process Technology

The combination of PLDA’s PCIe controller and MegaChips’ PHY will deliver a complete PCIe subsystem solution.

PLDA, the industry leader in PCI Express® IP solutions and MegaChips, a global semiconductor company specializing in ASIC Solution Services, today announced their collaboration to design a combined PCIe Controller IP and PHY IP solution. While the combination is currently targeting the TSMC 16nm process, the PCIe Controller/PHY solution will be easy to port to additional fabs and processes.

Come & meet us at TSMC OIP China 2018

 

TSMC OIP CHINA 2018
Fairmont Nanjing Hotel, Shanghai - October 30

Come meet the PLDA Team at TSMC Open Innovation Platform Ecosystem Forum 2018 in China !


It is a free event and it is an opportunity for you to discover our latest solutions, such as :

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