PCIe® 5.0 Link Training at 32 GT/s between PLDA's PCIe 5.0 controller and Broadcom PHY


The demonstration reaffirms the reliability and flexibility of the combined solution for SoC designers

PLDA, the industry leader in PCI Express® controller IP solutions has today unveiled their PCIe 5.0 demonstration.  The demo showcases stable PCIe 5.0 Link Training (32 GT/s) and exceptional signal integrity with a Broadcom® PCIe 5.0 PHY platform.

This solution is based on the XpressRICH® IP Controller for PCIe 5.0 combined with Broadcom’s PCIe 5.0 PHY IP. Several different setups demonstrate that the combined IPs provide exceptional signal integrity with, robust link training at 32 GT/s and stable backward compatibility at PCIe 4.0, PCIe 3.0, PCIe 2.0 and PCIe 1.0 speeds. The results of these tests is a quality guarantee for the SoC designers who choose the combined solution of PLDA’s PCIe 5.0 Controller and Broadcom’s PHY IP.

Demo Overview:

  • The Demonstration showcases exceptional signal integrity via an Eye scope provided by a SerDes Pattern Generator and PCIe 5.0 Tx Compliance Patterns monitored on a scope
  • Stable PCIe Link Training at 32 GT/s proven by a crosslink connection of 2 boards monitored using Xilinx Vivado ILA and a Viavi PCIe Analyzer
  • Backward PCIe compatibility at 16 GT/s, 8 GT/s, 5 GT/s, 2,5 GT/s demonstrated in a real environment.

"It’s a great milestone for PLDA technical teams to achieve stable PCIe Link Training at 32 GT/s,” said Stephane Hauradou, CTO at PLDA.“ The complexity and the challenges involved in reaching this result have evolved with the different PCIe generations and we wanted to further demonstrate our PCIe 5.0 solutions, even though they are already proven in silicon.”

For more information or to discover how PLDA solutions could work for your next PCIe 5.0 design:

Explore multiple silicon-proven PCIe 5.0 solutions from PLDA:

Tags: PCIe 5.0
Event date: Wednesday, October 21, 2020

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