Technical Article

1. Introduction

As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc.

The transition to PCIe 4.0 and 5.0 with increasing PCIe signaling speeds (16GT/s and 32GT/s) also augments the risk of errors due to tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g. crosstalk, line attenuation, jitter, etc.).

Computer systems as we know them have been built on the paradigm that the CPU-memory pair is fast while network and storage are slow. Over the years, these components developed their own language and interfaces that require layers of software to translate memory commands into network and storage commands and vice versa.

Until now, the speed of the CPU-memory pair relative to network and storage I/O was such that these software layers had minimal impact on system performance.

However, with Moore’s law in full effect, network and storage technologies are quickly catching up with CPU-memory speeds and the burden of generations of software layers now becomes significant.

PLDA’s strong Ecosystem and stringent 4-step integration process delivers pre-integrated and well-tested PCIe Controller and PHY solutions, solving many of the challenges and concerns faced by SoC designers

The race to launch devices supporting PCIe 4.0 started several months back. Designers face several challenges to release the product on D-Day:

PLDA’s PCIe Switch Solution provides a customizable and scalable switch design tailored for the needs of the PCIe switch marketplace. The PCIe® architecture has become a standard within the storage data centers due to the advantages it delivers in latency and performance. PCIe switches manage dataflow within a device, delivering the flexibility, scalability and configurability required to connect a large pool of drives or networks.

In that presentation, Rabih Eid, Support Manager, explains how to take advantage of PCIe Embedded Switch technology, reducing BOM, reusing existing designs, decreasing system power consumption and improving overall performance compared to an ASSP device.

Visit PLDA's PCIe Switch IP page for more information.

Methods to Fine-Tune Power Consumption of PCIe devices

A basic paradox of electronic evolution is the desire to enable the execution of more functions while consuming less power and silicon area. For PCIe® applications, this goal is not a new one. A PCI power management specification has been available since 1997, and PCI Express® has featured native power management since its initial release in 2002. In addition, there has always been a recognized need for low power in the mobile market.

PLDA, the company that designs and sells intellectual property (IP) cores and prototyping tools for ASICs and FPGAs, has optimized its ASIC intellectual property (IP) cores for the next generation of the ubiquitous and general purpose PCI Express® I/O specification, 4.0.  PLDA’s proven 3.0 architecture enables easy migration to PCIe 4.0, with no interface changes necessary, and preserves existing behavior for seamless integration.

By Philippe Legros, Product Design Architect, PLDA

Introduction

While server virtualization is being widely deployed in an effort to reduce costs and optimize data center resource usage, an additional key area where virtualization has an opportunity to shine is in the area of I/O performance and its role in enabling more efficient application execution.

Executive Summary:  To help leading storage companies address the booming demand of PCI SSD (Solid State Drive), PLDA enhances the end-to-end data integrity functionality of its PCIe soft IP products and showcases a NVMe demo on its hardware. 

PCIe, a key enabling technology in the Enterprise Solid State Drive Market