Reducing CXL Latency with PLDA and AnalogX


Certain applications and hardware types -- emerging memory, artificial intelligence/machine learning, and cloud servers, to name a few -- can realize significant performance advantages when a low latency interface is employed. The CXL (Compute Express Link™) standard was developed specifically as a low latency offshoot of the ever-popular PCIeTM (PCI ExpressTM), and is finding its footing in many of the applications listed.

Let’s compare typical latency of existing standards first. Data shown below is gathered from a variety of industry sources: 

From the chart, it's obvious why CXL is the high speed interface of choice for low latency applications. However, PLDA recognizes that there are applications in which CXL 2.0 latency remains a performance-limiting factor, even with CXL having the lowest latency amongst its contemporaries. Improving latency creates an opportunity for more optimized implementations for our customers, generally without cost or power implications in end systems.

To address this need, PLDA and AnalogX have announced the availability of an optimized CXL 2.0 controller and PHY solution. For comparison, here is the same chart with PLDA/AnalogX solution:

The 12ns latency is easily the lowest amongst all the interfaces, and ~50% lower than competing CXL solutions. 

This announcement is hugely impactful to system designers and chip architects who have latency as primary design concerns -- the optimized integration allows for lower latency without associated cost or power overheads. In fact, we believe this ultra-low latency will be hugely impactful in improving leading-edge systems.

The solution is based on PLDA’s XpressLINK Controller IP for CXL 2.0. Available today, this soft IP is a parameterizable controller designed for both ASIC and FPGA implementations. The XpressLINK Controller IP leverages PLDA's silicon proven XpressRICH Controller for PCIe 5.0 architecture for the path, and adds the CXL.cache and CXL.mem paths specific to CXL. XpressLINK exposes PLDA native Tx/Rx user interface for traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic. 

For more information on the solution, please contact us!


Event date: Thursday, June 3, 2021

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