There are significant advances in communication protocols happening all around us. The Peripheral Component Interconnect Express (PCIe) Gen 5 standard is delivering the needed device-to-device performance to support artificial intelligence and machine learning applications as well as cloud-based workloads. The rapidly evolving Compute Express Link (CXL) standard is delivering CPU-to-device and CPU-to-memory communication to enable next-generation data center performance. Both are critical enablers for next generation systems and require support in the form of semiconductor IP to be deployed. PLDA has made recent announcements regarding significant milestones for both PCIe and CXL, which is not a common occurrence. I wanted to look a bit closer at both of these announcements to see how PLDA is at the leading edge with advances in both PCIe 5.0 and CXL.
Both announcements were covered on SemiWiki. One is about the demonstration of successful PCIe 5.0 link training with PLDA’s PCIe 5.0 controller and Broadcom’s PHY. The other is about successful CXL interoperability with the pre-production Intel Xeon CPU, code named Sapphire Rapids. Standards support is all about interoperability and both of these announcements deliver proof of PLDA IP interoperability. Let’s take a closer look.
What was announced here was a demonstration showcasing a stable PCIe 5.0 link training (32 GT/s) featuring excellent signal integrity with a Broadcom® PCIe 5.0 PHY. PLDA used its XpressRICH® IP Controller for PCIe 5.0 with Broadcom’s PCIe 5.0 PHY IP. Several different scenarios were presented to highlight the exceptional signal integrity of the combined IPs. PLDA explained that the demo serves as a quality guarantee for SoC designers using the combined solution of PLDA’s PCIe 5.0 controller and Broadcom’s PHY IP.
The demonstration included:
- Exceptional signal integrity via an eye scope provided by a SerDes pattern generator and PCIe 5.0 Tx compliance patterns monitored on a scope
- Stable PCIe link training at 32 GT/s proven by a crosslink connection of two boards monitored using Xilinx Vivado ILA and a Viavi PCIe analyzer
- Backward PCIe compatibility at 16 GT/s, 8 GT/s, 5 GT/s, 2,5 GT/s that were demonstrated in a real environment
Stephane Hauradou, CTO at PLDA commented, “It’s a great milestone for PLDA technical teams to achieve stable PCIe Link Training at 32 GT/s. The complexity and the challenges involved in reaching this result have evolved with the different PCIe generations and we wanted to further demonstrate our PCIe 5.0 solutions, even though they are already proven in silicon.”
There is also a video available here that allows you to see the demo in action.
The CXL announcement was also about performance and interoperability. This time, between PLDA’s XpressLINK™ CXL IP, running on a PLDA FPGA-based add-in card and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors. The PLDA XpressLINK controller implements the CXL.io, CXL.cache, and CXL.mem sub-protocols as specified in the recently released CXL 2.0 specification and is already being designed-in at leading technology companies.
The demonstration was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. Stephane Hauradou commented, “Today’s demonstration of interoperability between PLDA’s XpressLINK CXL IP, which delivers the lowest latency in the industry, and a cutting-edge CPU like pre-production Intel Sapphire Rapids processor, is a critical step in assuring SoC designers of the robustness of our CXL implementation”.
Dr. Debendra Das Sharma, Intel Fellow and Director of I/O Technology and Standards Group, Data Center Group also commented, “CXL will be a foundational interconnect technology in the data centers and networks of the future. The availability of third party silicon IP like the PLDA XpressLINK CXL Controller IP lowers integration risks and helps ensure quicker proliferation of the CXL protocol across the industry ecosystem.”
PLDA XpressLINK and XpressLINK-SOC CXL IP are highly parameterized CXL controller soft IP designed to the latest CXL specification and architected for SoC, ASIC, and FPGA implementation. XpressLINK and XpressLINK-SOC are available for licensing immediately and are already designed at several leading-edge technology companies.
PLDA is a technical leader in high-speed Interconnect IP. These two recent announcements separated by only a few weeks demonstrate their commitment to supporting the latest standards with a focus on interoperability and robustness. To probe further:
- PCIe 5.0 Controller IP with a Native user interface Link PLDA website
- PCIe 5.0 Controller IP with AMBA® AXI user Interface
- PCIe 5.0 Multiport Transparent Switch IP
- PCS IP for PCIe 5.0
- XpressLINK-SOC CXL Controller with Configurable AMBA AXI Interconnect
- XpressLINK CXL Controller with CPI interconnect
You will clearly see that PLDA is at the leading edge with advances in both PCIe 5.0 and CXL.