On PCIe 6.0

Today, PLDA announced our PCIe 6.0 controller IP. This announcement builds on PLDA’s track record of being the high speed interface IP provider of choice.

As PCIe 6.0 is quite new, let’s run through a bit about how it differs from previous generations, and why this should matter to a system designer or chip architect as they consider their next generation designs.

PCIe (Peripheral Component Interconnect express) has existed for some time. You have to go all the way back to 1991 to examine the origins of PCIe, with Intel’s PCI standard for local busses. Appearing first in servers and later making its way to desktops, the PCI slot was a standard for a decade. As computing evolved, the industry recognized the need for the creation of a standard addressing a new bus architecture technology and internal connection of multiple chips. With that, PCIe was born, and in 2003, led by PCI-SIG, the 1.0 specification was ratified, offering a then blistering 2.5GT/s data rates.

Finding its footing in a variety of uses including solid-state drives, graphics card acceleration, and networking, PCIe has continued to evolve to suit the needs of the market. You can find PCIe is pretty much everywhere today; not only just in personal computers and servers for which PCIe was originally developed, but in places such as high end mobile, IoT devices, automobiles, medical devices, and many more.

The following chart shows the evolution of the specification over time:

Figure 1

Keen eyed readers may notice that the release cadence has increased greatly in the last few years. We will address this in a future articles. For now, let’s take a deeper look at the PCIe 6.0 specification and how it has evolved from past specifications.

First, as is usually the case with every new revision (looking at you, 2.x to 3.x), PCIe 6.0 doubles the bandwidth to 64 GT/s. PCI-SIG recognized early on that NRZ signal encoding, used since PCIe 1.0, simply isn’t capable of supporting the 64GT/s bandwidth PCIe 6 requires. Accordingly, the specification has transitioned to PAM4, a technique that allows carrying twice the number of bits over the same amount of time. However, the transition to PAM4 signal encoding introduces a significantly higher Bit Error Rate (BER), which prompted the adoption of a Forward Error Correction (FEC) mechanism to mitigate the higher error rate. Fortunately, this is lightweight enough to have minimal impact on latency. To note: while PAM4 signaling is more susceptible to errors, the channel loss is not affected compared to PCIe 5.0 due to the nature of the modulation technique, and so the reach of a PCIe 6.0 signal on a PCB will be the same as that of a PCIe 5.0 signal.

PCIe 6.0 also introduces FLIT mode, where packets are organized in Flow Control Units of fixed sizes, as opposed to variable sizes in past specification releases. The initial reason for introducing FLIT mode was that error correction requires working with fixed size packets; however, FLIT mode also simplifies data management at the controller level and results in higher bandwidth efficiency, lower latency, and smaller controller footprint. Let’s address bandwidth efficiency for a minute: with fixed-size packets, the framing of packets at the Physical Layer is no longer needed, that’s a 4-byte savings for every packet. FLIT encoding also does away with 128B/130B encoding and DLLP overhead from previous PCIe specifications, resulting in a significantly higher TLP efficiency, especially for smaller packets.

There are many other changes in PCIe 6; L0p mode, a new PIPE specification, and many new optional features. We look forward to exploring those in future articles.

 

Event date: Thursday, May 20, 2021

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