PLDA Announces XpressRICH4-AXI™ PCIe® 4.0 IP, Providing a High Performance and Reliable AXI Bridge for SoC designs

The newest addition to PLDA’s extensive line of advanced PCIe products provides the highest level of PCIe-to-AXI integration, preventing AXI deadlock with ordering rules management, while delivering full PCIe 4.0 performance in an AXI subsystem

SAN JOSE, Calif., March 13, 2017 -- PLDA, the industry leader in PCI Express® interface IP solutions, today announced their XpressRICH4-AXI™ PCIe® 4.0 IP, providing the industry’s best solution for integrating AXI and PCIe blocks.

Project teams who work on multicore SoC design face significant challenges as they strive to preserve native PCIe performance and prevent integrity errors while adding AXI capabilities. The historical approach to integrating AXI into PCIe applications involves adding an AXI block, but does not provide a true bridge. This approach requires the SoC designer to manually adjust errors and attempt to optimize PCIe and AXI performance unaided. In contrast, PLDA’s XpressRICH4-AXI has been optimized to provide a high-quality integration between the PCIe Interface and the AXI bus, enabling seamless interconnect, preventing AXI deadlock, and delivering full PCIe performance on the AXI side, while reducing the risk of errors in the AXI block.

PLDA’s XpressRICH4-AXI includes a 4th generation PCIe controller, which has been instrumental in over 350 successful tape-outs since 2001, helping to guarantee reliability, robustness, and first time silicon success. The integrated AXI bridge provides advanced features that extend AXI functionality, including:

  • Native PCIe features like AER (Advanced Error Reporting)
  • Ordering rules, including the ability to split into different size packets and merge between AXI and PCIe
  • Multiple flexible options to configure the AMBA AXI Interface, including multiple combinations of AXI Master, AXI Slave, and AXI Stream interfaces with different datapaths, such as 64-bits, 128-bits and 256-bits
  • A built-in AXI interconnect with up to 4 x Master/Slave, 4x Stream and Lite (Master/Slave) interfaces that can be combined together

According to Arnaud Schleich, CEO of PLDA, "With XpressRICH4-AXI and its enhanced bridge between the PCIe Interface and the AXI bus, PLDA has solved performance and integration issues that are not addressed by traditional IP supermarkets", Schleich added "XpressRICH4-AXI is the first PCIe IP block that delivers true PCIe 4.0 speeds in a multicore SoC based on the AXI AMBA specification protocol, offering significant time-to-market and cost-to-market advantages to PCIe 4.0 and AXI bus users."

More Information:

  • Meet the PLDA team at the TSMC Symposium Santa Clara on March 15, 2017 in Booth 804 and at TSMC Symposium China on March 28, 2017 in Booth 5.
  • View the complete XpressRICH4-AXI specification  
  • View a short video presentation and demo outlining the steps designers can take today to bring their PCIe 4.0 designs to completion.

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