Blog

Shanghai, China—Dec 11, 2018

Brite Semiconductor (“Brite”), a world-leading ASIC design service and DDR controller/PHY IP provider headquartered in Shanghai, China, today announced their collaboration with Naneng Microelectronics and PLDA to deliver a complete PCIe 2.0/3.0 solution based on SMIC’s 40nm and 55nm process technology.

Guosheng Wu, CEO of Naneng Microelectronics, said, “Collaboration between Naneng and Brite can effectively reduce the risks and costs of SoC design by providing a low power consumption and small-area PCIe-2.0/3.0 solution based on SMIC’s 40nm and 55nm process, that meets the latest PIPE specifications and supports 2.5G and 5G data rate. We are looking forward to working with Brite to provide customers with a global solution that offers high performance and low cost, while complying with the relevant standards.”

PLDA, the industry leader in PCI Express® controller IP solutions and Samtec, a privately held $800MM global manufacturer of a broad line of electronic interconnect solutions, today announced a demo of their combined PCIe 4.0 solution that delivers full PCIe 4.0 bandwidth (16 GT/s) over copper or optical fiber at minimal cost.

The solution is based on a PLDA PCIe 4.0 acquisition board running PLDA’s PCIe 4.0 controller IP combined with Samtec’s FireFly™ Micro Flyover System™. This demo suggests a solution to overcoming the inherent limitations of maintaining PCIe 4.0 performance over long distances without changing the motherboard technology or using costly retimers.

SAN MATEO, Calif., Nov. 26, 2018 -- SiFive, the leading provider of commercial RISC-V processor IP, today announced that PLDA, the leader in PCIe and CCIX Controller IP solutions has joined the DesignShare™ ecosystem. Through this collaboration, PLDA will provide its rich suite of XpressRICH core IP that enables high-speed connectivity solutions for many applications like enterprise storage, networking, high-performance computing and artificial intelligence to name a few.

As cloud computing and deep learning accelerators drive faster advances in the PCIe roadmap, existing hardware designs cannot support the higher speed signals over the same distances. The PCIe 1.0 specification allowed signals to travel as much as 20 inches over traces in mainstream FR4 boards, even while passing through two connectors. In contrast, today’s quicker 16 GT/s PCIe 4.0 signals will peter out in under six inches and without going over any connectors.

Computer systems as we know them have been built on the paradigm that the CPU-memory pair is fast while network and storage are slow. Over the years, these components developed their own language and interfaces that require layers of software to translate memory commands into network and storage commands and vice versa.

Until now, the speed of the CPU-memory pair relative to network and storage I/O was such that these software layers had minimal impact on system performance.

However, with Moore’s law in full effect, network and storage technologies are quickly catching up with CPU-memory speeds and the burden of generations of software layers now becomes significant.

The combination of PLDA’s PCIe controller and MegaChips’ PHY will deliver a complete PCIe subsystem solution.

PLDA, the industry leader in PCI Express® IP solutions and MegaChips, a global semiconductor company specializing in ASIC Solution Services, today announced their collaboration to design a combined PCIe Controller IP and PHY IP solution. While the combination is currently targeting the TSMC 16nm process, the PCIe Controller/PHY solution will be easy to port to additional fabs and processes.

PLDA Announces Integration of their PCIe 3.0 Controller IP into Kazan Networks’ NVMe Over Fabric™ Fuji ASIC, Providing a Dramatic Increase in Scalability and Flexibility for Storage Applications

PLDA and Kazan to Highlight their Products at Flash Memory Summit 2018 in Santa Clara, CA from August 7 – 9, 2018

PLDA and HPE collaborate on Gen-Z silicon IP to enable a robust ecosystem of Gen-Z component providers to power memory-driven systems and solutions.

Palo Alto, Calif., July 26, 2018 – Hewlett Packard Enterprise (HPE) and PLDA®, an industry leader in high-speed interconnect IP, today announced a joint collaboration to meet the challenges of next-generation connectivity for advanced workloads. Gen-Z is a new open interconnect protocol and connector developed by the Gen-Z Consortium to solve the challenges associated with processing and analyzing huge amounts of data in real time. HPE and PLDA are working together to develop Gen-Z semiconductor IP designed to the Gen-Z Core Specification 1.0.

PLDA has been successfully delivering PCI and PCI Express IP for more than 20 years.

With over 6,200 licenses, PLDA has established a vast customer base and the world’s broadest PCIe ecosystem. PLDA has maintained its leadership over four generations of PCI Express specifications, enabling customers to reduce risk and accelerate time to market for their ASIC and FPGA based designs. PLDA provides a complete PCIe solution with its IP cores, FPGA boards for ASIC prototyping, PCIe BFM/testbenches, PCIe drivers, and APIs.

PLDA is a global company with offices in North America (San Jose, California), Europe (France, Italy, and Bulgaria), and Asia (China, Taiwan).

PLDA to Demonstrate Industry’s First PCIe® 4.0 Switch Platform with Multiple Downstream Ports during PCI-SIG DevCon 2018