XpressSWITCH Embedded Switch IP for PCIe running on a Bittware 250S+ Near Storage Accelerator card and allowing up to 4 NVMe SSDs to be accessed simultaneously at full PCIe speed.
The combination of PLDA XpressSWITCH Switch IP for PCIe and Bittware 250s+ Storage FPGA card is the ideal solution for building intelligent storage accelerators integrating multiple NVMe SSDs in a compact PCIe form factor.
PLDA, the industry leader in PCI Express® IP and interconnect solutions, today announced a major PCIe 5.0 design win on cutting edge 5nm process node. PLDA’s PCIe 5.0 Controller IP was selected not only for its solid design and unmatched compatibility with popular PCIe PHYs, but also for PLDA’s best-in-class tech support, its ease of customization and PLDA’s integration expertise.
Here, we look at 6 reasons to choose the profession of Electronic Verification Engineer instead.
Discover how Inspector can be used all along your hardware validation cycle
In support of immediate Gen-Z development, PLDA has released a detailed datasheet enabling designers to begin architecting and designing Gen-Z enabled SoCs. This PLDA Gen-Z IP datasheet includes the key information required for initial design including supporting features, interface description and micro architecture, gate count, performance metrics, and more.
1. Introduction
Modern enterprise workloads in AI and data analytics are driving the need for new compute and storage architectures in IT infrastructures. The growing use of accelerators (GPUs, FPGAs, custom ASICs) and emerging memory technologies (3D XPoint, Storage Class Memory, Persistent Memory), and the need to better distribute and utilize these resources are fueling the transition to composable/disaggregated infrastructures (CDI) in data centers.
In this video, we show how SoC designers can leverage the vDMA engine built into PLDA’s XpressRICH-AXI PCIe controller to manage concurrent high performance data traffic between a virtualized PCIe device and multiple Virtual Machines running on the host platform.
1. Introduction
Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.
In this article, we look into the various protocols by providing a brief history, a quick technical comparison, and the latest deployment status. We also offer our perspective on the evolution of these protocols.
The explosion in data traffic due to the advent of Artificial Intelligence, machine learning, automotive and IoT prompts for new System-on-Chip architectures that allow system developers to build high-performance applications that are able to ingest and process huge amounts of heterogeneous data.
1. Introduction
As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc.
The transition to PCIe 4.0 and 5.0 with increasing PCIe signaling speeds (16GT/s and 32GT/s) also augments the risk of errors due to tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g. crosstalk, line attenuation, jitter, etc.).
