PLDA, the industry leader in PCI Express® interface IP solutions, today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP. PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency. This level of performance is highly anticipated by developers of leading edge applications in Artificial Intelligence (AI) and Machine Learning (ML), data center storage and networking, and High Performance Computing (HPC).
The accelerated transition from PCIe 4.0 to PCIe 5.0 is paving the way for hyperscale data centers in the race to 100G and 400G Ethernet. The PCI-SIG consortium expects rev. 1.0 of the PCIe 5.0 specification to be released in 2019.
PLDA’s XpressRICH5 provides full support of the PCIe 5.0 rev. 0.7 specification (32 GT/s) for ASIC, SoC and FPGA implementation, and allows seamless migration from FPGA prototyping to ASIC/SoC production with the same RTL code base. PLDA’s XpressRICH5 controller IP also features:
- A Core architecture extended to support the 512-bit data path required for handling PCIe 5.0 x16 throughput comfortably
- Advanced built-in Reliability/Availability/Serviceability (RAS) features that enable safe and reliable deployment of IP in mission-critical SoCs. RAS features include:
- PIPE interface snoop module, providing real-time access to unscrambled traffic for easier debug.
- Programmable LTSSM, ACK, NACK, and REPLAY timers, allowing safe operation with non-compliant devices and systems.
- Programmable Flow Control (FC) update priority, delivering performance tuning and optimization.
A vibrant ecosystem of PHY IP vendors and Verification IP (VIP) vendors working hand in hand with PLDA to offer complete pre-validated solutions for PCIe 5.0, thus providing customers with a wide range of options.
According to Arnaud Schleich, CEO of PLDA, “PCIe 5.0 is a significant step forward in the ever-increasing need for faster semiconductor devices. PLDA’s extensive experience in PCIe development began with the very first iterations of PCI in the mid 90s. This legacy of expertise assures our customers that PLDA’s XpressRICH5 will provide them the reliability and ease of integration they need as they transition to a new platform.”
- For information on PLDA’s new XpressRICH5 Controller IP, please visit PLDA’s PCIe 5.0 IP webpage
- Visit PLDA at an upcoming industry event:
- PCI-SIG DevCon 2018. June 5 and 6, 2018 in Santa Clara, CA: PLDA will be demonstrating their latest products. To register and attend PCI-SIG DevCon please visit https://pcisig.com/events/pci-sig-developers-conference-2018.
- DAC 2018. June 24-28, 2018 in San Francisco, CA: PLDA’s Sr. FAE, Trupti Gowda, will present "Will PCIe 5.0 become ubiquitous in tomorrow’s SOCs?" To register and attend DAC 2018, please visit https://dac.com