Come & meet us at PCI-SIG Fall Virtual DevCon 2020

PCI-SIG Fall Virtual DevCon  - October 12-27

Virtual developers conference

PLDA will showcase their solutions for PCIe technologies such as:

In addition, we will provide a technical presentation about the topic: “Prototyping and Hardware Validation of PCIe 5.0 designs at 32GT/s: Challenges and Solutions”

The number of silicon chips supporting PCIe 5.0 is already ramping up at leading edge foundries, while PCIe 4.0 only begins to hit the market with the first commercial platforms. Nonetheless, the data rate promised by the PCIe 5.0 technology is reaching a physical limit at 32GT/s speed, introducing a slew of constraints at various levels: PCB track topology restrictions, PCS requirements, etc. In this presentation we list and explain the challenges facing PCIe 5.0 hardware validation & prototyping, and propose ways to address these challenges.

Let's discuss your projects and issues!
We will be happy to introduce our products and share our knowledge.

Register here:

Event's dates: 
Sessions Posted: Wednesday, October 12th- 23th, 2020
Live Q&A Sessions: Thursday, October 26th-27th, 2020 at:

  • PDT: 5:00pm – 8:00pm
  • CST: 8:00am – 11:00am
  • JST: 9:00am – 12:00pm
Event date: Monday, October 12, 2020

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