Wireless VR Accelerator ASIC

Overview

This customer developed an ASIC for accelerating a proprietary software video CODEC in hardware in order to reduce the latency and latency jitter to the Virtual Reality headsets. The chip is manufactured on SMIC 40LL process.

PLDA Inside

The ASIC uses PLDA XpressSWITCH switch IP with one Gen3 x4 upstream port to the host CPU and two downstream ports. One downstream port connects to an embedded Gen3 x4 endpoint (using PLDA XpressRICH3-AXI controller IP) responsible for the CODEC function. The second downstream port connects off-chip to a PCIe Gen3 x2 radio transmitter endpoint responsible for transferring encoded streams to the VR headsets.

Why PLDA?

The customer selected PLDA XpressSWITCH and XpressRICH3-AXI for the following reasons:

  • Proven integration with the PHY IP selected (PHY partner M31)
  • Availability of a PCI-SIG compliant switch IP with low latency
  • Ability to prototype the entire chip on FPGA, including the switch IP
  • Flexible/configurable AXI interfaces and integrated DMA in XpressRICH3-AXI for easy application development
  • Availability of on-site training to help with integration and silicon bring-up