NVMe-oF Bridge ASIC

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Overview

The 100G NVMe-oF bridge ASIC is designed specifically to enable NVMe JBOFs to connect directly to an NVMe-oF network, via a standard x16 PCIe slot in a JBOF.  The chip is manufactured on TSMC 28 HPC process.

PLDA Inside

The SoC uses PLDA XpressRICH controller IP for PCIe 3.1 as the PCIe interface to the host CPU subsystem. The IP operates as a Gen3 x16 endpoint interface, or can be configured as 2 x Gen3 x8 connections via port bifurcation.

Why PLDA?

PLDA IP was selected based on the following criteria:

  • Proven integration with Synopsys PCIe PHY
  • Availability of port bifurcation wrappers
  • Maturity of PLDA XpressRICH Controller IP for PCIe 3.1

NVMe Controller SoC Platform

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Overview

EpoStar’ PCIe-NVMe SSD controller platform (Libra) is compliant with NVM Express 1.2 specification and targets both enterprise and client SSD markets. It features EpoStar’s Meissa NVMe controller core and Alcyone LDPC error correction core to enable low-power and cost-effective SSD controllers that support 1x/1y/1z MLC/TLC and 3D NAND. For more information about the Libra platform, visit http://www.epostar-elec.com/products_Platform.html.

PLDA Inside

The platform uses PLDA XpressRICH-AXI controller IP for PCIe 3.x as the PCIe interface to the host CPU subsystem. The IP operates as a Gen3 x4 endpoint interface with an option to support 8 lanes. The IP’s configurable AXI interface allowed a seamless connection to the SoC’s AXI fabric.

Why PLDA?

Epostar selected PLDA IP based on the following criteria:

  • Flexible, user-configurable AXI interconnect
  • Handling of AMBA AXI ordering rules inside the IP vs. in application logic
  • Performance achieved across the AXI interfaces
  • Top-notch technical support from a dedicated and knowledgeable support team
  • Proven integration with the PHY IP selected (PHY partner GUC)

32G Fiber Channel Host Bus Adapter SoC

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Overview

This 256G (4x64G) Fiber Channel HBA SoC is engineered for modern networked storage systems. The chip is manufactured using TSMC 16nm FinFET process.

PLDA Inside

The SoC uses PLDA XpressRICH controller IP for PCIe 4.0 as the PCIe interface to the host CPU subsystem. The IP operates as a Gen4 x16 endpoint interface. The IP is used in Transaction Layer Bypass mode allowing for ultra low latency and the reuse of a proprietary transaction layer.

Why PLDA?

PLDA IP was selected based on the following criteria:

  • Availability of a TL bypass mode allowing customer to implement its own Transaction Layer and ensure existing driver and firmware compatibility
  • Support for SR-IOV with a large number of virtualized functions
  • Flexibility of the PIPE interface in term of supported width and frequency
  • Flexibility in the partitioning and implementation of the Receive/Transmit buffers for SR-IOV support