The customer developed a silicon chip for the tunneling of PCIe traffic over HDBaseT, providing a whole-car backbone network infrastructure, for optimized sensor fusion, ADAS and infotainment. HDBaseT supports multi-gigabit transfers over up to 50 feet of unshielded twisted pair cable. The chip is manufactured on TSMC 28HPC process.
The ASIC uses PLDA XpressRICH controller IP for PCIe 3.1 that can be statically configured as a Gen3 x4 upstream or downstream port, depending on where the chip is used in the system.
The customer selected PLDA IP based on the following criteria:
- Availability of design expertise during the architecture phase
- Superior IP metrics (gate count, latency) compared to competing solutions
- Proven integration with the PHY IP selected (Cadence PHY)
- Proven track record enabling PCIe bridging and switching designs