Deep Learning SoC for AI training acceleration

Overview

The Deep Learning Processing Unit SoC is the building block of an AI training system intended to accelerate neural net training by 1000x vs. GPU based solutions. The chip is manufactured using TSMC 16nm FinFET process.

PLDA Inside

The SoC uses PLDA XpressRICH3-AXI controller IP as the PCIe interface to the host CPU subsystem. The IP operates as a Gen3 x16 endpoint interface. The IP’s configurable AXI interface allowed a seamless connection to the SoC’s AXI4 fabric.

Why PLDA?

PLDA IP was selected based on the following criteria:

  • Availability of an AXI interconnect with built-in DMA allowing for AXI to AXI transfers
  • Strict support for AMBA AXI ordering rules to avoid deadlocks
  • Overall performance achieved across the AXI interfaces
  • Proven integration with the PHY IP selected (PHY partner Analog Bits)