PLDA XpressRich2 PCI Express endpoint, root port, switch, bridge all-in-one is a silicon-proven semiconductor IP designed for PCI Express Gen1 and Gen2 implementations. The XpressRich2 "universal" PCI Express controller implements all of the digital layers defined by the PCI Express 2.0 Specification and is fully backward compatible with PCI Express® 1.1.

What's unique about our IP?

• Guaranties seamless integration with a wide range of PCI Express® PHY IP.
• Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
• Software Design Environment with device drivers, API, and example GUI applications with source code.
  
• We offer professional services to quickly and reliably customize our IP to fit any specific needs
• Our IP customization GUI (Wizard)
  
• Free evaluation program including the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

IP Features and Deliverables

• PCI Express® IP core in synthesizable Verilog and VHDL RTL source code
  • Complies to the PCI Express® Base Specification, revision 2.0
    • Backwards compatible with the PCI Express® Base Specification, revision 1.1
  • Supports Endpoint, Root Port, dual-mode, Switch upstream and downstream, Bridge
    • x1, x4, x8
  • Includes Physical, Data Link, and Transaction layers
    • Optimized for high throughput and minimal latency
    • Optional Physical Coding Sub-layer (PCS)
  • 64-bit data path
    • Tx/Rx based per-VC user interface
    • Configurable user clock frequency
  • PIPE interface to PHY
    
    • 16-bits: 125 Mhz in Gen1 mode, 250 Mhz in Gen2 mode
      
    • 8-bits: 250 Mhz in Gen1 mode, 500 Mhz in Gen2 mode
  • Up to 8 Virtual Channels
    
  • Maximum Payload Size up to 4KB
  • Number of outstanding requests: 32 (up to 2048 with Phantom Function)
  • Configurable Receive and Retry buffers
  • Type 0 and Type 1 Configuration spaces
  • Up to 6 BARs plus expansion ROM available for Endpoints
  • All I/O and Memory windows implemented for Root, Switch, and Bridge configurations
  • Power Management
    • All Power States
    • Legacy PCI Power Management
    • Native Active State Power Management (ASPM) L0s, L1
  • Also Supports...
    
    • Multi-Function
    • MSI-X
    • Multiple MSI generation
    • ECRC (End-to-End Cyclic Redundancy Check), except for Switch configurations
    • Advanced Error Reporting (AER)
    • ECC protection on Rx buffer
    • Extensive test/debug interface
    • Lane reversal
• PCI Express® Testbench simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• PCI Express® IP simulation models
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• ASIC synthesis scripts
  • Synopsys Design Compiler, Cadence RTL Compiler
• Reference design
  • Synthesizable Verilog and VHDL RTL source code
  • Simulation & Synthesis environments and scripts
• Software Design Environment
  • 32-bit/64-bit Linux, 32-bit Windows XP PCI Express® device driver
    • Source code available as an option
      
  • C source code API
  • PCI Express® GUI tools and C++/Java source code
• Complete documentation

Avalaible Documentation

Document Name	Version
Reference Manual	Dec 19, 2008