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Home >>Interface IP>>SuperSpeed USB>>for Altera FPGA>>USB 3.0 Host Controller

 USB 3.0 Host ControllerPrint Friendly

Free DownloadPLDA USB 3.0 Host Controller is a high performance, low gate count semiconductor IP that adds SuperSpeed USB Host connectivity to Altera FPGAs. The controller is compliant to the Intel xHCI specification and implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0.

What's unique about our IP?
  • Supports Stratix IV GX , Cyclone III
  • USB 2.0 backward compatible
  • Guaranties seamless integration with the supported FPGA 5.0 Gbit transceivers and discrete USB 3.0 PHY chips
  • Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
  • Our IP customization GUI (Wizard)
  • Free evaluation program that includes the same deliverables and technical support as the licensed IP.
  • The IP comes with our industry acclaimed technical support provided by the IP team.
Supported Altera FPGA families and Configurations
  • Stratix IV GX, E, GT with embedded 5.0 Gbit transceivers
  • Cyclone III with external USB 3.0 PHY chip: contact us
IP Features and Deliverables


  • USB 3.0 Host IP core in synthezisable Verilog RTL (encrypted or source code)
    • Includes Physical, Link, and Protocol layers
    • Includes xHCI Host Controller
    • Complies to the USB 3.0 Specification, revision 1.0
    • Full support for legacy USB 2.0
      • With PLDA USB 2.0 Core Layer
      • Or with 3rd-party USB 2.0 IP through intelligent multiplexing
    • Core frequency: 125 Mhz
    • Available user interfaces include AMBA 2 AHB or AMBA 3 AXI
    • Asynchronous clocking between Core and user interface logic (CDC)
    • Configurable buffer sizes
    • USB 3.0 PIPE interface to PHY (8-,16-, or 32-bit)
    • Full Power Management support (U1,U2,U3)
      • LFPS support
    • Support Isochronous and Bulk Stream traffic
  • USB 3.0 Host IP simulation models
  • USB 3.0 Testbench simulation libraries
  • PIPE wrappers and Physical Coding Sub-layers (PCS)
    • For the supported Altera FPGA devices with embedded PCI Express® 5.0 Gbit transceivers
    • For the supported external USB 3.0 PHY chips
  • Configuration assistant GUI (Wizard)
    • Multi-platform JAVA based
  • Complete documentation

Available Documentation

Document Name Version
Reference Manual Contact us
Product Brief February 24, 2010