PLDA USB 3.0 Device Controller is a high performance, low gate count semiconductor IP that adds SuperSpeed USB device connectivity to Altera FPGAs. The controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0.

What's unique about our IP?

• Supports Cyclone III, Cyclone IV FPGA
  
• Complete mass storage class reference design kit fully implemented in hardware
  • No additional CPU required
    
• Supports TI's USB 3.0 Transceiver (TUSB1310)
  
• USB 2.0 backward compatible
  
• Complete Quartus projects and reference designs to get you started easily

Supported Altera FPGA families and Configurations

• Cyclone III , Cyclone IV
  
• Stratix II, Stratix III, Stratix IV
  

IP Features and Deliverables

• USB 3.0 Device IP core in synthezisable Verilog RTL (encrypted or source code)
  • Includes Physical, Link, and Protocol layers
  • Includes Device Controller
  • Complies to the USB 3.0 Specification, revision 1.0
  • Full support for legacy USB 2.0
  • Core frequency: 62.5 Mhz
  • USB 3.0 PIPE interface (16-bit)
  • USB 2.0 ULPI interface
  • Full Power Management support (U1,U2,U3)
    • LFPS support
  • Up to 16 IN and OUT endpoints
• USB 3.0 Device IP simulation models
• Interface to TI's TUSB1310
  
• USB 3.0 Testbench simulation libraries
• Reference design: Mass Storage Class Device
  • Synthesizable Verilog RTL source code
  • Simulation environment
  • FPGA synthesis and Place-and-Route environment
• Complete documentation

 Available Documentation

Document Name	Version
Reference Manual	April, 07th 2010
Product Brief	February, 24th 2010