DMA for PCIe Integr. Block - PLDA
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Home >>Interface IP>>PCI Express®>>for Xilinx FPGA>>DMA for PCIe Integr. Block

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PLDA EZDMA2 DMA for PCI Express® Integrated Block is a high performance, fully configurable DMA controller soft IP engineered to add multi-channel DMA capability to Xilinx's Virtex and Spartan families of FPGAs with integrated PCI Express® blocks. EZDMA2's interface is the native user interface on PLDA's XpressLite2 IP, and is backward compatible with PLDA's PCI and PCI-X IP user interfaces.

Learn more about EZDMA2 DMA IP for Xilinx Integrated Block for PCI Express®.

What's unique about our IP?
  • Guaranties seamless integration and operation.
  • Reference designs to get you started and allow you to deploy your applications. Check out our FPGA Design Kits section.
  • Software Design Environment with device drivers, API, and example GUI applications with source code
  • We offer professional services to quickly and reliably customize our IP to fit any specific requirement.
  • Our IP customization GUI (Wizard)
  • Free evaluation program that includes the same deliverables and technical support as the licensed IP.
  • The IP comes with our industry acclaimed technical support provided by the IP team.
Supported Xilinx FPGA families and Configurations
  • PCI Express® 2.0 in Gen2 mode (5.0 GT/sec)
    • Virtex-6 LXT, SXT: x1, x4, x8
  • PCI Express® 2.0 in Gen1 mode (2.5 GT/sec)
    • Virtex-5 LXT, SXT, TXT, FXT: x1, x4, x8
    • Virtex-6 LXT, SXT: x1, x4, x8
    • Spartan-6 LXT: x1 (x4 using XpressLite2 soft IP)
IP Features and Deliverables

EZDMA for Xilinx PCIe Integrated Block Block Diagram

  • EZDMA2 IP core in synthesizable Verilog and VHDL RTL encrypted or clear source code
    • Up to 2KB Max Payload Size
    • EZDMA2 user's interface
      • 64-bit or 128-bit data path
      • Up to 8 DMA channels
      • Up to 7 Outstanding Read Requests
      • Per DMA channel scatter-Gather support with host based descriptors
      • Integrated DMA arbitration optimized for maximum throughput
  • PCI Express® Testbench simulation libraries
  • EZDMA2 IP core simulation models
  • Configuration assistant GUI (Wizard)
    • Multi-platform JAVA based
  • Endpoint reference design
    • Synthesizable Verilog and VHDL RTL source code
    • Simulation environments and scripts
    • FPGA synthesis environments and scripts
  • Software Design Environment
    • 32-bit/64-bit Linux, 32-bit Windows XP PCI Express® device driver binary
      • Source code version available as an option
    • C source code API
    • PCI Express® GUI tools and C++/Java source code
  • Complete documentation

Available Documentation

Document Name Version
Product Brief May 11, 2009
Reference Manual April 30, 2010
Getting Started Manual April 30, 2010