PLDA XpressRich PCI Express® root port, switch or advanced endpoint is a high performance, silicon proven semiconductor soft IP engineered for PCI Express® interfacing with Xilinx FPGAs. The XpressRich "universal" PCI Express® controller implements all of the digital layers defined by the PCI Express® 1.1 Specification.  We recommend our XpressRich universal controller IP for designs requiring Root Port or switch support or advanced features such as multi-VC or multi-function.

• Guaranties seamless integration and operation.
• Reference designs to get you started and allow you to deploy your applications. Check out our FPGA Design Kits section.
• Software Design Environment with device drivers, API, and example GUI applications with source code
• We offer professional services to quickly and reliably customize our IP to fit any specific requirement.
• Our IP customization GUI (Wizard)
  
• Free evaluation program that includes the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

• PCI Express® 2.0 in Gen1 mode (2.5 GT/sec)
  
  • Virtex 5 FXT/LXT/SXT/TXT, Virtex 4 FX: x1, x4
  • Virtex 5 FXT/LXT/SXT/TXT, Virtex 4 FX/LX
    
    • Genesys Logic GL9714: x4
    • NXP PX1012A: x1
    • TI xIO1100: x1
  • Virtex 6 : x1,x4 at PIPE level

• PCI Express® IP core in synthesizable Verilog and VHDL RTL encrypted or clear source code
  • Compliant with the PCI Express® Base Specification, revision 2.0
    
    • Backward compatible to the PCI Express® Base Specification, revision 1.1
  • Supports Endpoint, Root Port, dual-mode, Switch upstream and downstream, Bridge
    • x1, x4
  • Includes Physical, Data Link, and Transaction layers
    • Optimized for high throughput and minimal latency
  • 64-bit data path
    • Tx/Rx based per-VC user interface
    • Configurable user clock frequency
  • PIPE interface to FPGA PHY
    • 16-bit/125Mhz
  • Up to 8 Virtual Channels*
  • Maximum payload size up to 4KB*
  • Configurable Receive and Retry buffers
  • Number of outstanding read requests: 32 ( up to 2048 with Phantom Function)
  • Type 0 and Type 1 Configuration spaces
  • Up to 6 BARs plus expansion ROM available for Endpoints
  • All I/O and Memory windows implemented for Root, Switch, and Bridge configurations
  • Power Management
    • All Power States
    • Legacy PCI Power Management
    • Native Active State Power Management (ASPM) L0s, L1*
  • Also Supports:
    • Multi-Function*
    • MSI-X
    • Multiple MSI generation
    • ECRC (End-to-End Cyclic Redundancy Check), except for Switch configurations*
    • Advanced Error Reporting (AER)
    • ECC protection on Rx buffer
    • Extensive test/debug interface
    • Lane reversal
• PCI Express® Testbench simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• PCI Express®  IP core simulation models
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• PIPE wrappers and Physical Coding Sub-layers (PCS)
  • For the supported Xilinx FPGA families with embedded PCI Express® transceivers
  • For the supported external PCI Express® PHY chips
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• Endpoint reference design
  • Synthesizable Verilog and VHDL RTL source code
  • Simulation environments and scripts
  • FPGA synthesis/PAR environments and scripts
• Software Design Environment
  • 32-bit/64-bit Linux, 32-bit Windows XP PCI Express® device driver binary
    • Source code option available
  • C source code API
  • PCI Express® GUI tools and source code (C++, Java)
• Complete documentation