PLDA AMBA 2 AHB to PCI Express® Bridge is a high performance, highly-configurable, silicon-proven semiconductor IP that adds PCI Express® connectivity to AMBA 2 AHB enabled SoCs. The bridge IP is compliant to the PCI Express® rev. 2.0 specification and AMBA 2 AHB rev. 2.0 specification.

What's unique about our IP?

• Free Testbench is provided
  
• Guaranties seamless integration with a wide range of PCI Express® PHY IP.
• Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
• Software Design Environment with device drivers, API, and example GUI applications with source code
• We offer professional services to quickly and reliably customize our IP to fit any specific requirement.
• Our IP customization GUI (Wizard)
• Free evaluation program that includes the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

IP Features and Deliverables

• PCI Express® to AMBA 2 AHB Bridge IP core in synthesizable Verilog and VHDL RTL source code
  
  • Compliant to the PCI Express® Specification rev. 2.0
    
    • Includes PCI Express® Physical, Link, and Protocol layers
    • PCI Express® interface configurable as Root Port, Endpoint, or dual-mode
    • PCI Express® x1, x2 (Gen1 2.5G and Gen2 5.0G)
    • PIPE compliant Physical layer, 16-bit/125Mhz or 8-bit/250Mhz
    • Low power ASPM L0s and L1 for maximum power savings
    • Up to 1KB Max. Payload Size
    • Optional support for AER and ECRC
  • Supports ExpressCard Specification
  • Supports Hot Plug
  • Compliant to the AMBA 2 AHB Specification rev. 2.0
    • Includes AMBA AHB bridging and interface logic
    • 32-bit AHB master and slave interfaces
  • User defined AHB frequency
• PCI Express® BFM simulation libraries
  • Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• AMBA AHB Testbench simulation libraries
  • Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• ASIC synthesis scripts
  • Cadence RTL Compiler, Synopsys Design Compiler
• Software design Kit
• Reference design
  • Synthesizable Verilog and VHDL RTL source code
  • Simulation environments and scripts
• Complete documentation

 

Available Documentation

Document Name	Version
Reference Manual	February 28, 2010
Product Brief	November 14, 2008