PLDA AMBA 2 AHB to PCI Bridge is a high performance, highly-configurable, silicon-proven semiconductor IP that adds PCI connectivity to AMBA 2 AHB enabled SoCs. The bridge IP is compliant to the PCI Local Bus rev. 2.3 specification and AMBA 2 AHB rev. 2.0 specification.

What's unique about our IP?

• Free Testbench is provided
  
• Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
• Software Design Environment with device drivers, API, and example GUI applications with source code
• We offer professional services to quickly and reliably customize our IP to fit any specific requirement.
• Our IP customization GUI (Wizard)
  
• Free evaluation program that includes the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

IP Features and Deliverables

• PCI to AMBA AHB Bridge IP core in synthesizable Verilog and VHDL RTL source code
  • Pin-selectable host-bridge, add-on device, or dual mode host/add-on
  • Compliant to the PCI Specification rev. 2.3
    • 32-bit and 33/66 Mhz PCI bus interface
  • CardBus and mini PCI support in both add-on and host-bridge mode
  • Built-in PCI arbiter can control up to 7 PCI devices
  • Built in DMA
  • PCI masters can directly transfer data to/from AHB devices
  • Concurrent DMA read, DMA write, AHB-to-PCI and PCI-to-AHB transfers
  • Compliant to the AMBA 2 Specification rev. 2.0
    • Includes AMBA AHB bridging and interface logic
    • 32-bit AHB master and slave interfaces
  • AHB masters can directly transfer data to/from PCI devices
  • User defined AHB frequency
    
• PCI Testbench simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• AMBA AHB Testbench simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• ASIC synthesis scripts
  • Cadence RTL Compiler, Synopsys Design Compiler
• Software design Kit
• Reference design
  • Synthesizable Verilog and VHDL RTL source code
  • Simulation environments and scripts
• Complete documentation

Available Documentation

Document Name	Version
Reference Manual	February 21, 2009
Testsuite Reference Manual	February 20, 2008