PLDA AMBA 3 AXI to PCI Express® Bridge is a high performance, highly-configurable, silicon-proven semiconductor IP that adds PCI Express® connectivity to AMBA 3 AXI enabled SoCs. The bridge IP is compliant to the PCI Express® rev. 2.0 specification and AMBA 3 AXI rev. 1.0 specification.

What's unique about our IP?

• Free Testbench is provided
• Guaranties seamless integration with a wide range of PCI Express® PHY IP.
• Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
• Software Design Environment with device drivers, API, and example GUI applications with source code
• We offer professional services to quickly and reliably customize our IP to fit any specific requirement.
• Our IP customization GUI (Wizard)
  
• Free evaluation program that includes the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

IP Features and Deliverables

• AMBA 3 AXI to PCI Express® Bridge IP core in synthesizable Verilog and VHDL RTL source code
  • Compliant to the PCI Express® Specification rev. 2.0
    
    • Includes PCI Express® Physical, Link, and Protocol layers
    • PCI Express® interface configurable as Root Port, Endpoint, or dual-mode/shared silicon
    • PCI Express® x1, x4
    • PIPE compliant Physical layer, 16-bit/125Mhz
    • 1 or 2 Virtual Channels
    • Up to 2KB Maximum Payload Size
    • 1 to 3 64-bit Base Address Registers (BAR)
    • Configurable Receive, Transmit, and Retry buffer size
    • Low power ASPM L0s and L1 for maximum power savings
    • Legacy PCI Power Management
    • MSI and INT messaging
    • AER
    • ECRC generation/check
  • Supports ExpressCard Specification
    • CLKREQ#
  • Compliant to the AMBA 3 Specification rev. 1.0
    • Includes AMBA 3 AXI bridging and interface logic
    • 64-bit AXI master and slave interfaces with 32-bit addressing
  • User defined AXI frequency
  • 2, 4, or 8 outstanding master read request and 16 write requests
  • 4, 8, or 16 outstanding slave read requests and 2, 4, or 8 write requests
• PCI Express® BFM simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• ASIC synthesis scripts
  • Cadence RTL Compiler, Synopsys Design Compiler
• Software design Kit
• Reference design
  • Synthesizable Verilog and VHDL RTL source code
  • Simulation environments and scripts
• Complete documentation

Available Documentation

Document Name	Version
Reference Manual	April 14, 2010