PLDA PCI Express® to PCI Bridge is a high performance, highly-configurable, silicon-proven semiconductor IP that transparently bridges a PCI Local Bus to a PCI Express® hierarchy. The bridge IP is compliant to both the PCI Express® rev. 2.0 specification and the PCI Local Bus rev. 2.3 specification.

What's unique about our IP?

• Free Testbench is provided
  
• Guaranties seamless integration with a wide range of PCI Express® PHY IP.
• Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
• Software Design Environment with device drivers, API, and example GUI applications with source code
• We offer professional services to quickly and reliably customize our IP to fit any specific requirement.
• Our IP customization GUI (Wizard)
  
• Free evaluation program that includes the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

IP Features and Deliverables

• PCI Express® to PCI Bridge IP core in synthesizable Verilog and VHDL RTL source code
  
  • Compliant to the PCI Express® Specification rev. 2.0
    
    • Transparent forward bridge
    • PCI Express® x1, x4
      
  • Compliant to the PCI Local Bus Specification rev. 2.3
    • CardBus and mini PCI support in both add-on and host-bridge mode
  • Built-in PCI arbiter can control up to 7 PCI devices
  • Built in DMA
  • PCI masters can directly transfer data to/from AHB devices
  • Concurrent DMA read, DMA write, AHB-to-PCI and PCI-to-AHB transfers
  • Compliant to the AMBA Specification rev. 2.0
    • Includes AMBA AHB bridging and interface logic
    • 32-bit AHB master and slave interfaces
    • Integrated arbiter controls up to 7 devices
  • Transparent forwarding memory transactions across the bridge
  • I/O, prefetchable memory, non-prefetchable memory windows
  • VGA/ISA Enable decoding
  • Several outstanding requests and buffer queues allow for increased throughput
    
  • Conversion and forwarding of Type0/Type1 Configurations transactions
    
  • Automatic error management and logging
    
  • Automatic transaction ordering (PCI and PCI Express® ordering rules)
    
  • Interrupt/MSI forwarding
• PCI Testbench simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• PCI Express® BFM simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• ASIC synthesis scripts
  • Cadence RTL Compiler, Synopsys Design Compiler
• Software Design Kit
• Complete documentation
  
• (optional) FPGA prototyping environment
  
  • Synthesis/PAR constraints
  • Bistream file
    

Available Documentation

Document Name	Version
Reference Manual	Contact us
Build History	Contact us