PLDA USB 3.0 Host Controller is a high performance, low gate count, xHCI compliant semiconductor IP designed for SuperSpeed USB host implementations in ASIC or Structured ASIC and engineered for 130 nm process nodes and smaller geometries. The controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0. User interfaces options include AMBA 2 AHB and AMBA 3 AXI.

What's unique about our IP?

• Guaranties seamless integration with a wide range of USB 3.0 PHY IP.
• Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section
• Professional services to quickly and reliably customize our IP to fit any specific requirement.
• USB 2.0 backward compatible
• Our IP customization GUI (Wizard).
• Free evaluation program that includes the same deliverables and technical support as the licensed IP.
• The IP comes with our industry acclaimed technical support provided by the IP team.

IP Features and Deliverables

• USB 3.0 Host IP core in synthezisable Verilog RTL source code
  • Includes Physical, Link, and Protocol layers
  • Includes xHCI controller
    • Can be removed to allow custom programming interfaces
  • Complies to the USB 3.0 Specification, revision 1.0
  • Full support for USB 2.0
    • With PLDA USB 2.0 Core Layer
    • Or with any USB 2.0 IP through intelligent multiplexing
  • Optional Root Hub available for multi-port implementation
  • Configurable Core frequency: 125, 250, or 500Mhz
  • Available user interfaces include AMBA 2 AHB, AMBA 3 AXI
  • Asynchronous clocking between Core and user interface logic (CDC)
  • Configurable buffer sizes
  • USB 3.0 PIPE interface to PHY (8-,16-, or 32-bit)
  • Full Power Management support (U1,U2,U3)
    • LFPS support
  • Support Isochronous and Bulk Stream
    
• USB 3.0 Testbench simulation libraries
• USB 3.0 Host IP simulation models
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• ASIC synthesis scripts (Synopsys Design Compiler)
• Reference design: PCI Express® based USB 3.0 Host Bus Adapter (HBA)
  • Synthesizable Verilog RTL source code
  • Simulation environments and scripts
• Complete documentation

Available Documentation

Document Name	Version
Product Brief	November 13, 2008
Reference Manual	Contact us