Interface
IP
SoC
IP
FPGA
Design Kits
Client account
What's inside the box ?
  • IP Customization GUI
  • Flexible license terms
  • Free Testbench and SDK
  • Reference Design
  • Risk-free evaluation program
  • Technical support by bus experts
Home >>Interface IP>>PCI/PCI-X>>for Altera FPGA>>PCI-X and PCI

 PCI-X and PCIPrint Friendly

Free Download

PLDA PCI-X & PCI IP Core provides an integrated solution for interfacing your application with 32-bit and 64-bit PCI-X / PCI peripheral devices.

What's unique about our IP?
  • Easy customization with the PCI Wizard's user interface and on-line help.
  • PCI Wizard has built-in support for VHDL and Verilog.
  • All features can be parameterized, removing all unused logic
  • Full plug-and-play supportGuaranties seamless integration with a wide range of PCI Express® PHY IP.
  • Reference designs to get you started and allow you to prototype all or part of your ASIC/SoC. Check out our FPGA Design Kits section.
  • Software Design Environment with complete drivers, API, GUI applications and clear source code example
  • We offer professional services to quickly and reliably customize our IP to fit any specific needs
  • Our IP customization GUI (Wizard)
  • Free evaluation program including the same deliverables and technical support as the licensed IP.
  • The IP comes with our industry acclaimed technical support provided by the IP team.
IP Features and Deliverables



  • PCI and PCI-X IP core in Verilog and VHDL source code for Altera devices
    • 32-bit/64-bit PCI-X & PCI master/target interface
    • Supports bus speed up to 133 MHz
    • Up to 4 independent DMA channels
    • Supports up to 4KB burst transfers
    • Multi-function core can implement up to 2 independent functions
    • Full support for 64-bit addressing
    • PCI-X & PCI Specification 2.0a mode 1 compliant
    • PCI Specification 3.0 compliant
    • Supports PCI power management
    • Built-in support for in-site programming through JTAG interface
    • Supports Message Signalled Interrupts
  • PCI Express® Testbench simulation libraries
    • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
  • Configuration
    • Supports all required and optional type 0 configuration registers
    • Up to 6 BARs plus expansion ROM can be implemented
    • Up to 32 user defined configuration registers
  • Reference design
    • Synthesizable Verilog and VHDL RTL source code
    • Simulation & Synthesis environments and scripts
  • Software Design Environment
    • 32-bit/64-bit Linux, 32-bit Windows XP PCI Express® device driver
      • Source code available
    • C source code API
    • PCI Express® GUI tools
  • Complete documentation

Avalaible Documentation

Document Name Version
Reference Manual August 11, 2010
Testbench Reference Manual August 11, 2010
Getting Started August 11, 2010